I. Field of the Disclosure
The field of the disclosure relates generally to computer memory, and particularly to static random access memory (SRAM) global bitlines for providing memory read access outputs for a memory array.
II. Background
Processor-based computer systems include memory for data storage. Different types of memory exist, each possessing certain unique features. For example, static random access memory (SRAM) is a type of memory that can be employed in processor-based computer systems. SRAM can store data without the need to periodically refresh the memory, unlike dynamic read access memory (DRAM) for example. An SRAM contains a plurality of SRAM bitcells (also referred to as “bitcells”) organized in rows and columns in an SRAM data array. For any given row in an SRAM data array, each column of the SRAM data array will contain an SRAM bitcell in which a single data item or bit is stored. Access to a desired SRAM bitcell row is controlled by a corresponding wordline for read and write operations. To read data from an SRAM bitcell, a wordline is asserted to select a desired row of SRAM bitcells corresponding to a memory address of a memory access request. For a read operation (also referred to as a “memory read access”), data read from the selected SRAM bitcell is placed on a local bitline to be provided to an SRAM data output. For a write operation, data to be written to the SRAM bitcell is placed on the local bitline for the SRAM bitcell. Complementary local bitlines may also be employed to improve noise margins in the SRAM bitcell. Further, an SRAM data array may have multiple data sub-arrays or banks that each contain their own access circuitry and dedicated local wordlines and bitlines allowing for accesses in multiple data sub-arrays at the same time.
An SRAM may also employ the use of global bitlines in addition to local bitlines corresponding to particular bitcells. Global bitlines can be employed to aggregate the local bitlines of the SRAM bitcells for each column of an SRAM data array so as to output data corresponding to only one bitcell in each column of the SRAM data array at a time. This aggregation is possible because the wordline can only select one row of an SRAM data array for each read operation. Thus, only the bitcell of each column that corresponds to the row selected by the wordline will have its data read onto its local bitline for a given read operation. No data values are lost due to aggregation since only the local bitlines corresponding to the selected row, and reflected on the global bitlines, possess data read from a bitcell. This aggregation provides a smaller load on the SRAM data output as compared to a load created when providing the local bitlines for every bitcell to the SRAM data output. This smaller load allows the SRAM data output to consist of transistors that require lower drive current, thus reducing power consumption within the SRAM.
While employing a global bitline scheme in an SRAM may provide a smaller output load on SRAM data outputs, employing global bitlines in an SRAM can have certain disadvantages. For example, employing a global bitline scheme in an SRAM may result in unintended power glitches during SRAM read operations. A power glitch can occur when the global bitline is incorrectly set to a logical ‘1’ value (e.g., voltage of a voltage supply rail) for a certain length of time when the output should equal a logical ‘0’ value (e.g., voltage of ground). Such a power glitch can be the result of certain circuit timing characteristics. Moreover, the errant logical ‘1’ value on the global bitline, caused by a power glitch, increases the power consumption of the SRAM.
One solution to prevent power glitches in an SRAM due to such circuit timing characteristics involves delaying the transfer of data read from the local bitlines so that such data is not prematurely placed onto a global bitline. However, delaying the transfer of data in this way can cause the global bitline to receive the data later in time, thus increasing the latency of a memory read operation. This increased latency incurred for SRAM read operations may not be desirable or may cause the SRAM to be outside desired memory access time specifications. Thus, it would be advantageous to employ global bitlines in an SRAM to reduce the load on the SRAM data output while reducing or avoiding power glitches arising during SRAM read operations without increasing the latency of such operations.